25 Feb 2013 Update
I know people have been waiting on an update for awhile. The simple fact of the matter is there hasn't been any solid updates to offer. I know people are desperate and starving for information and I wish I could provide new information every day, but some days there just isn't new information. Luckily there is some new information today. It's not the best information (such as we are shipping today!) but it is at least an update.
We had expected the bumping to be done by now, as per the previous update(s). That has not been completed yet. There are a number of reasons why this is the case, and we are not pleased with any of them. The bumping facility, which we have no direct contact with, did not complete the NRE on the timeline we had spoke to the packaging facility about. As I've written in previous posts, we are dealing with such an accelerated time scale that all of these facilities simply aren't used to dealing with. It's been a learning experience for both us and for the facilities we are using. The upside, such as it is, is that going forward, we will have all the large, time sucking hurdles already out of the way and the rest of the chips should breeze through without issue, as all the NRE, tooling, design, planning and machines will already be configured for what we need.
Since Friday we have been, in a word, agonizing over how to make up for lost time. Obviously, we can't make up for all the lost time, but what we have decided is to effectively burn (this is not a technical term, I simply mean we are using one of the wafers for testing instead of creating chips out of it) one of the initial six wafers for testing. This is definitely not something we wanted to do, as it will reduce our initial chip count from a potential 6000 to 5000 chips for the first set of wafers. We are doing this because it will buy us 7 - 12 days for the second set of wafers (and the remaining set of wafers down the road). The time frame between the 1st set of wafers and the 2nd set of wafers should be reduced to a matter of a few days.
Why are we burning the wafer, what advantage does that give us and how can that accelerate the timeline? As many of you already know, we have had the 2nd set of wafers holding with the last layers being unfinished until we confirm we have everything the way we want it on the first set of wafers. We've already started the process to continue laying down layers up until about the last 5 layers or so - by burning one of our precious wafers, we can send it to the ASIC engineers who can essentially wire bond it manually and test the chips, but the wafer will become useless for creating usable chips. By doing this, they will verify that everything is how it needs to be and we can give the foundry the go-ahead to finish the second set as well as the bulk of the chips immediately. The second set of wafers should be done and on their way to us by the time we get chips in house in KC, and the bulk wafers should be done shortly after that.
The test wafer is already on it's way to the ASIC labs and should arrive tomorrow. Presumably it will take a better part of the day to get everything situated and for the testing to begin, so I don't expect to hear anything until late Tuesday or sometime on Wednesday assuming everything goes well. In the meantime, the bumping facility will be bumping the remaining 5 wafers, which should be shipping out on Friday to the packaging house, whom we are paying extra to stay on for the weekend and start the packaging process. We expect at least some of the chips to be on their way to Chicago by Tuesday, where they will be mounted and sent out to our engineers and KC for testing and final MCU programming. At that point, once the MCU programming is confirmed we'll begin assembling the units. Right now, I'm planning on a week from Friday to be the day, but I'm just gonna say that's subject to change at the moment, although I don't anticipate a change right now.
The ASIC team has promised me pictures of the wafer tomorrow, Tuesday the 26th. As soon as I get those, I will be posting them. As soon as I hear something with regards to the chip testing, I will be posting that as well. If I'm not posting an update, it's because there's nothing new to report.
I finally went to bed around midnight last night and these pics rolled in around 2AM, so I wasn't up to post them.
However, here's a couple pics of the test wafer at the testing facility. They will be putting the chips through testing today (Wednesday) and we should have results back sometime later tonight. I will post when I have more information on that front.
28 Feb 2013 Update
The ASIC team has been working all day on testing the various aspects of the chip. There have been no problems so far and all 16 engines hash properly at 250 MHz. Full range tests are scheduled for tomorrow to see how high we can the engines past 500 MHz (the nominal speed the chips are slated to run at).
No update on the bumping at the moment, but I should have one tomorrow as to the disposition of that.
4 March 2013 Update
Today the bumped wafers were confirmed at the packaging facility and they have been "bumped nicely," so all is well as far as bumping goes. Packaging is currently scheduled to be done on Wednesday, although that's subject to change, I don't see any reason that is going to change at the moment.
The chips achieved 350 MHz hashing on 4 engines as well. We are going to have to wait until the chips are packaged to take the chips higher than that with more cores, as the test rig is not able to supply enough power and there are some wire bond issues that make it unstable beyond that. Once the chips are packaged, they will be tested more fully. Regardless, the chips are hashing properly and all IO appears to be correct, which is the important part. I will update when further testing is complete.
Timeline for the second set of 6 wafers is currently scheduled several days out after we have a successful test of the packaging (they'll have to make their way through bumping and packaging as well) and then the remainder is scheduled for ~7 days after that. I can't be more specific with regards to a date on the 6 wafers yet, as I don't have specific dates. I will update once I do.
7 March 2013 Update
The chips are the packaging facility and being packaged. I don't currently have any further updates beyond that at this point. They should be done sometime today or tomorrow, but that is, of course, subject to change. I will update when I have further information.
7 March 2013 Update Part Deux - Electric Boogaloo
Got an update from the packaging house. As some of you may know already, there was some trouble with the fiduciary marks and the current alignment of the machines for the substrates. That was worked out and the machines were re-calibrated today to use the current markings. I am going to be flying to California either Friday night or Saturday morning and moving the packaged chips to the ASIC teams location as well as making sure they get off to Chicago as fast as possible. We expect the packaging to be complete either Saturday night or Sunday. The packaging house is working on the weekend to finish the job.
I will update when I have more information, but it looks like Saturday or Sunday for the full testing to begin. Simultaneously, the chips will be in Chicago being mounted on the boards, so we should see boards starting to arrive in KC early to mid next week.
15 March 2013 Update
It's been a long couple days here at the labs! Trying to test the chip in the test rig has been exceptionally trying and it turns out it's due to a bad socket on the tester. Initially we were concerned there might be a problem with the bumping or substrate, but fortunately we had tested the chips prior with the wire bonding technique, so we knew they worked. Getting the test boards made proved to be fortuitous as well, since we were able to bypass the test rig completely and bring the chips up on the board. By doing so, we were able to finally identify that the problem was related directly to the test rig and not any intermediate process or step.
Bringing a chip to life in situ on a board is not the easiest thing, so it has been slow going. The chip was responding properly on the board late this afternoon and we will be picking up the process in the morning. We hope to have a more complete test by Saturday night or Sunday sometime. Meanwhile, we will also be hard soldering a chip into place for use in the test rig and replacing the socket to allow the bulk testing to finish. In some other positive news, we've not found a single bad chip yet, which could mean our yield rate will be exceptionally high... maybe we just got lucky out of the 50 chips we have available on boards so far, but it seems unlikely. So that may mean the vast majority of our chips will be usable.
So the good news is the boards work, the chips work, the bumping works, the substrate works. We just need to nail down a bit more with the firmware and we should be able to conduct a full test and start shipping.
I will be posting another update as soon as I have more information. Needless to say it's been a pretty busy and stressful last few days here, and some script kiddie deciding to DDoS our sites this morning didn't help matters. All connectivity problems should be resolved now and we will keep people updated as time allows.
Last edited by BFL_Josh; 03-15-2013 at 11:09 PM.
28 March 2013 - Mini-Update
I had wanted to post a video tonight, but wasn't able to make that happen, so let me apologize for that in advance. As some of you may know from the chatbox, we have been working diligently to get these ASICs out the door. We've been tracking down a power issue these last few days and have it isolated to a few key systems. In the interest of time, we are planning on potentially scaling back units hashing speed as required to accommodate the extra power and shipping multiple units to those that want their units right now. If would would prefer to wait for a unit after we've made some changes to the systems that need a bit of tweaking, we will be happy to put your shipment on hold. However, if you'd rather have the units right now at an increased power usage, we will ship you as many units as required to get you to the hashrate your purchased, if we end up having to scale back any given class of unit to fit within the power envelope of the current board design.
We have the current design hashing, and as I said, I had hoped to have a video of a unit hashing here in KC, but I wasn't able to bring that all together tonight, but hopefully I can get it posted up tomorrow or by this weekend. I will update as soon as I have more news to share, with a video.
If you absolutely do not want a unit that is consuming more power than expected, you can let us know you'd like to wait for a revised unit or you are welcome to request a refund. If you'd rather have your units shipped regardless of increased power usage, we will still guarantee your hashrate by shipping you however many units are required to achieve your purchased hashrate. There is no need to contact us right now if you are not concerned about the power usage and just want your units shipped ASAP. Even with the increased power demand on these first units, they will still out perform any competing products by a very wide margin in terms of power and megahash/J.
Again, we apologize for the delay, but we are almost there.